Thick gate oxide quality is adversely affected when another, thinner gate oxide is formed from a portion of the thick oxide by partially removing that portion of the thick gate oxide and by a subsequent cleaning process. Additionally, thick gate oxide integrity (GOI) failure will occur.
Further, there is not available a reliable method of forming triple gate oxides, each with a different thickness, in MOS/CMOS devices on the same wafer.
A method of forming such triple, or greater, gate oxides on the same wafer will have potential application when device dimensions, or design rule, becomes smaller and smaller which may well require different operating voltages for the input and output of transistors. The lower the voltage, the thinner the gate oxide. The gate oxide of a lower voltage device, i.e. having a thinner gate oxide, cannot withstand the higher voltage of an older technology device and will wear out, or fail, too quickly.
U.S. Pat. No. 5,926,708 to Martin describes a method of manufacturing an integrated circuit with two or more gate oxide thicknesses on the same wafer. A first gate oxide layer is formed on a semiconductor wafer. A first layer of polysilicon is formed over the first gate oxide layer and a polish stop film is formed over the first polysilicon layer. The polish stop and first poly layer are etched to expose a portion of the first gate oxide layer. The exposed first gate layer portion is stripped to expose a portion of the underlying wafer. A second gate oxide layer, thicker than the first gate oxide layer, is then formed on the exposed wafer portion and a gate conductor material layer is formed over the second gate oxide layer, blanket covering the first poly layer. The gate conductor layer is planarized by CMP to remove it form the first poly layer, forming a gate conductor.
U.S. Pat. No. 5,953,599 to El-Diwany describes a method of forming a thin layer of gate oxide for low-voltage transistors that support the logic operations of a CMOS device, and a thick layer of gate oxide for high-voltage transistors that support the analog operations of the device.
U.S. Pat. No. 5,432,114 to O describes a method of fabricating an IGFET integrated circuit (IC) having two gate dielectric layers with different parameters. The O process is typically used for fabrication of dual voltage CMOS integrated circuits. The IC may include high voltage transistors having a first gate dielectric thickness and low voltage transistors having a second gate dielectric thickness.